H. J. Siegel is the George T. Abell Endowed Chair Distinguished Professor of Electrical and Computer Engineering at Colorado State University (CSU), where he is also a Professor of Computer Science. He is Director of the CSU Information Science and Technology Center (ISTeC), a university-wide organization for enhancing CSUs activities pertaining to the design and innovative application of computer, communication, and information systems. Before joining CSU, he was a Professor at Purdue University from 1976 to 2001. He received two B.S. degrees from the Massachusetts Institute of Technology (MIT), and the M.A., M.S.E., and Ph.D. degrees from Princeton University. He is a Fellow of the IEEE and a Fellow of the ACM. Prof. Siegel has co-authored over 380 published technical papers in the areas of parallel and distributed computing. He was a Coeditor-in-Chief of the Journal of Parallel and Distributed Computing, and was on the Editorial Boards of the IEEE Transactions on Parallel and Distributed Systems and the IEEE Transactions on Computers.

Dr. Moinuddin Qureshi is a research staff member at IBM T.J. Watson Research center. His research interest includes computer architecture, scalable memory systems, fault tolerant computing, and analytical modeling of computer systems. Qureshi received his PhD from the University of Texas at Austin in 2007. While at IBM, he contributed to the design of efficient caching algorithms for Power 7 processors. Qureshi holds four US patents and has more than a dozen publications in flagship architecture conferences.

David H Bailey (http://crd.lbl.gov/~dhbailey) is a mathematician and computer scientist. He received his B.S. in mathematics from Brigham Young University in 1972 and his Ph.D. in mathematics from Stanford University in 1976. He worked for 14 years as a computer scientist at NASA Ames Research Center, but since 1998 has been the Chief Technologist of the Computational Research Department at the Lawrence Berkeley National Laboratory.
Bailey is perhaps best known as a co-author (with Peter Borwein and Simon Plouffe) of a 1996 paper that presented a new formula for (pi). This BaileyBorweinPlouffe formula permits one to calculate binary or hexadecimal digits of pi beginning at an arbitrary position, by means of a simple algorithm. The formula was discovered by Simon Plouffe using a computer program written by Bailey. More recently (2001 and 2002), Bailey and Richard Crandall showed that the existence of this and similar formulas has implications for the long-standing question of "normality" whether and why the digits of certain mathematical constants (including pi) appear "random" in a particular sense. Bailey is a long-time collaborator with Jonathan Borwein (Peter's brother). They are co-authors of numerous papers and three books and on experimental mathematics.
Bailey also does research in numerical analysis and parallel computing. He has published studies on the fast Fourier transform, high-precision arithmetic, and the PSLQ algorithm (used for integer relation detection). He is a co-author of the NAS Benchmarks, which are used to assess and analyze the performance of parallel scientific computers. He currently is a co-leader (with Robert Lucas of ISI/USC) of the Performance Engineering Research Institute a research consortium to study high-end computer performance, funded by the SciDAC program of the U.S. Department of Energy.
Bailey is a recipient of the Sidney Fernbach award from the IEEE Computer Society, as well as the Chauvenet Prize and the Hasse Prize from the Mathematical Association of America. In 2005 he was a nominee for the $100,000 Edge of Computer Science Prize. In 2008 he was a co-recipient of the ACM Gordon Bell Prize.

Enric Musoll graduated in computer science from the Polytechnic University of Catalonia at Barcelona (European Union) in 1993 and received the PhD in computer science from the same university in 1996 on the topic of low-power design. Since then, Enric has held industry positions in computer architecture, design and verification in National Semiconductor Corp. and in several start-up companies, in particular ConSentry Networks, where he has been instrumental in the design, tape-out and bring-up of the company's family of massive multi-core packet processors. His research interests include high-level synthesis techniques for low power and low-power high-performance computer architectures. Enric holds 31 US granted patents and 28 publications in peer-reviewed international conferences and journals.

Brian Vinter is Professor of Computer Science at University of Copenhagen, where he heads the Centre for eScience. Vinter is a master of computer-engineering from Aalborg University in Denmark and PhD from Tromsø¸ University, Norway. Professor Vinters professional interests are centered on High Performance Computing, Grid systems and eScience in general.

Professor Jean-Luc Gaudiot received the Diplôme d'Ingénieur from the École Supérieure d'Ingénieurs en Electronique et Electrotechnique, Paris, France in 1976 and the M.S. and Ph.D. degrees in Computer Science from the University of California, Los Angeles in 1977 and 1982, respectively.
He is currently a Professor in the Electrical Engineering and Computer Science Department at the University of California, Irvine. He was Chair of the Department from 2003 to 2009. During his tenure, the department underwent significant changes. These include the hiring of twelve new faculty members (three senior professors) and the remarkable rise in the US News and World Report® rankings of the Computer Engineering program from 42 to 28 (46 to 36 for the Electrical Engineering program).
Prior to joining UCI in January 2002, he was a Professor of Electrical Engineering at the University of Southern California since 1982, where he served as Director of the Computer Engineering Division for three years. He has also designed distributed microprocessor systems at Teledyne Controls, Santa Monica, California (1979-1980) and performed research in innovative architectures at the TRW Technology Research Center, El Segundo, California (1980-1982). He frequently acts as consultant to companies that design high-performance computer architectures, and has served as an expert witness in patent infringement and product liability cases. His research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published over 200 journal and conference papers. His research has been sponsored by NSF, DoE, and DARPA, as well as a number of industrial organizations.
In January 2006, he became the first Editor-in-Chief of the IEEE Computer Architecture Letters, a new publication of the IEEE Computer Society, which he helped found to the end of facilitating short, fast turnaround of fundamental ideas in the Computer Architecture domain. From 1999 to 2002, he was the Editor-in-Chief of the IEEE Transactions on Computers. In June 2001, he was elected chair of the IEEE Technical Committee on Computer Architecture, and re-elected in June 2003 for a second two-year term.
Dr. Gaudiot is a member of AAAS, ACM, and IEEE. He has also chaired the IFIP Working Group 10.3 (Concurrent Systems). He was co-General Chairman of the 1992 International Symposium on Computer Architecture, Program Committee Chairman of the 1993 IFIP Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, the 1993 IEEE Symposium on Parallel and Distributed Processing (Systems Track), the 1995 Parallel Architectures and Compilation Techniques Conference (PACT 95), the High Performance Computer Architecture conference in 1999 (HPCA-5), and the 2005 International Parallel and Distributed Processing Symposium.
In 1999, he became a Fellow of the IEEE, For Contributions to the Programmability and Reliability of Dataflow Architectures. He was elevated to the rank of AAAS Fellow in 2007, For Distinguished Contributions to the Design and Analysis of Highly Efficient Multiprocessor and Memory System Architectures.
Dr. Gaudiot is an avid pilot and he brings to his leisure time his love for teaching by being a flight instructor (both primary and instrument).
Home page

Dr. D. R. Avresky is currently a President of the International Research Institute on Autonomic Network Computing (IRIANC), Boston, MA, USA/ Munich, Germany. IRIANC has been founded by professors from USA, France, Germany, Italy, Austria, Spain and Portugal.
In total, Dr. D. R. Avresky has published more than 118 papers. Dr. D. R. Avresky has supervised 13 PhD students. He has been funded by the National Science Foundation (two consecutive grants), Hewlett Packard Research Labs, Compaq, Tandem, NASA, Motorola Research Labs, Bell Labs, and others institutions in USA. In addition, four books and five book chapters have been published: "Dependable Network Computing," Kluwer Academic Publishers, 2000, USA, "Fault -Tolerant Parallel and Distributed Systems," Kluwer Academic Publishers, December 1997, USA, "Fault- Tolerant Parallel and Distributed Systems," Computer Society Press, USA, December 1995, "Hardware and Software Fault-Tolerance in Parallel Computing Systems, Ellis Horwood, Simon&Schuster International Group, Chichester, England, August 1992.
Dr. Avresky has been a Co-guest editor of five IEEE journals: 1) IEEE Transactions on Parallel and Distributed Systems, special issue on Dependable Network Computing, February 2001 ; 2) IEEE Transactions on Computers, special issue on "Embedded Fault-Tolerant Systems," February 2002.;3) IEEE Micro, Computer Society,special issue on "Embedded Fault-Tolerant Systems, USA, 2001.;4) IEEE Micro, Computer Society, USA, special issue on "Embedded Fault-Tolerant Systems," September/October 1998.;5) IEEE Transactions on Computers , Guest Co-Editor , Special Section on " Autonomic Network Computing", July 2008.
He served as a reviewer for The IEEE Transactions Computers, IEEE Transactions on Parallel and Distributed systems and other refereed journals. As well, Dr. D. R. Avresky is a member of the Program Committee and a reviewer for numerous IEEE conferences. He was a Guest Co-Editor of The Journal of Supercomputing, Kluwer Academic Publishers, USA on "Embedded Fault-Tolerant Systems," May 2000. Dr. D. R. Avresky served on the Editorial Board of the The Journal of Supercomputing, Kluwer Academic Publishers, MA, USA.
Dr. D. Avresky is a founder and a Program/Steering Committee Chairman of The IEEE International Symposium on Network Computing and Applications (NCA*), Cambridge, MA, (from 2002 through 2010). Steering Committee Chair of The Cloud Computing Conference , Munich, Germany, 2009, General Chair of The 2005 IEEE International Conference on Cluster Computing, Boston MA, USA. He is Founder and a Program Chair of The Annual IEEE International Workshop of Fault-Tolerant Parallel and Distributed Systems (FTPDS - now DPDNS), (held in conjunction with The IEEE International Parallel & Distributed Processing Symposium (IPDPS) ) from 1996 through 2204. D. Avresky is a Chair of the Steering Committee for DPDNS from (from 2005 through 2009). Founder and a Program Chair of the IEEE Workshop on Embedded-Fault Tolerant Systems (EFTS), (1996, Dallas, TX), (1998, Boston, MA) and (2000, Washington, DC.)
His research interests are fault tolerance, network computing, distributed systems, emerging technologies (autonomic and cloud computing.)

Daniel S. Katz is the TeraGrid GIG Director of Science, and a Senior Fellow in the Computation Institute (CI) at the University of Chicago and Argonne National Laboratory. He is also an affiliate faculty member at the Center for Computation and Technology (CCT), Louisiana State University (LSU), where he was previously Director for Cyberinfrastructure Development from 2006 to 2009, and Adjunct Associate Professor in the Department of Electrical and Computer Engineering at LSU. He was at JPL from 1996 to 2006, in a variety of roles, including: Principal Member of the Information Systems and Computer Science Staff, Supervisor of the Parallel Applications Technologies group, Area Program Manager of High End Computing in the Space Mission Information Technology Office, Applications Project Element Manager for the Remote Exploration and Experimentation (REE) Project, and Team Leader for MOD Tool (a tool for the integrated design of microwave and millimeter-wave instruments). From 1993 to 1996 he was employed by Cray Research (and later by Silicon Graphics) as a Computational Scientist on-site at JPL and Caltech, specializing in parallel implementation of computational electromagnetic algorithms. His research interests include: numerical methods, algorithms, and programming applied to supercomputing, parallel computing, cluster computing, distributed computing, and embedded computing; and fault-tolerant computing. He received his B.S., M.S., and Ph.D degrees in Electrical Engineering from Northwestern University, Evanston, Illinois, in 1988, 1990, and 1994, respectively. His work is documented in numerous book chapters, journal and conference publications, and NASA Tech Briefs.
Home Page

After earning his Ph.D. degree in computer science at RWTH Aachen University (Germany) in 2003, Felix Wolf spent more than two years as a postdoctoral researcher at the University of Tennessee. In 2005, he became head of a research group at the Jülich Supercomputing Center. Since 2009, he leads the Laboratory for Parallel Programming at the German Research School for Simulation Sciences in Aachen. His research concentrates on aspects of parallel performance including software tools for the performance analysis of large-scale applications. As a computer-science professor at RWTH Aachen University, he teaches parallel programming and simulation software engineering.

Jean-Marc Pierson: Since September 2006, Jean-Marc Pierson serves as a University Professor in Computer Science at the University Paul Sabatier, Toulouse 3 (France). Jean-Marc Pierson received his PhD from the ENS-Lyon, France in1996. He was an Associate Professor at the University Littoral Cote-d'Opale (1997-2001) in Calais, then at INSA- Lyon (2001-2006). He is a member of the IRIT Laboratory and leads a group of 6 researchers. His main interests are related to large-scale distributed systems, funded by several projects in Grids and Pervasive environments, with applications in biomedical informatics. He serves on several PCs in the Grid and Pervasive computing area. His researches focus on security, cache and replica management, monitoring and more recently energy aware distributed systems. He is chairing the COST Action IC0804 on "Energy efficiency in Large Scale Distributed Systems". For more information, please visit http://www.irit.fr/~Jean-Marc.Pierson/

Carlo Bertolli has published research papers in the context of high- performance parallel programming, related to fault tolerance, adaptivity and dynamicity. He is currently a young researcher (post-doc) of an Italian national base research project on emergency management applications. In the last year he has focused his research also on pervasive computing environments and autonomic systems.

Bradford Chamberlain is a Principal Engineer at Cray Inc., where he works on parallel programming models, focusing primarily on the design and implementation of the Chapel language in his role as technical lead for that project. Brad received his Ph.D. in Computer Science & Engineering from the University of Washington in 2001 where his work focused on the design and implementation of the ZPL parallel array language, particularly on its concept of the region --- a first-class index set supporting global-view data parallelism. While at UW, he also dabbled in algorithms for accelerating the rendering of complex 3D scenes. Brad remains associated with the University of Washington as an affiliate faculty member and recently co-led a seminar there that focused on the design of Chapel. He received his Bachelor's degree in Computer Science from Stanford University in 1992.

Christos Kozyrakis is an Associate Professor of Electrical Engineering & Computer Science at Stanford University. He received a BS degree from the University of Crete (Greece) and a PhD degree from the University of California at Berkeley (USA), both in Computer Science. Christos works on architectures, runtime environments, and programming models for parallel computer systems. At Berkeley, he developed the IRAM architecture, a novel media-processor system that combined vector processing with embedded DRAM technology. At Stanford, he lead the Transactional Coherence and Consistency (TCC) project at Stanford that developed hardware and software mechanisms for programming with transactional memory. He has also investigated security systems and power management techniques for data-centers. Currently, he is a member of the Pervasive Parallelism Lab, a multi-faculty effort to make parallel computing practical for the masses. Christos is the Willard R. and Inez Kerr Bell faculty scholar at Stanford University. He is also a senior member of the ACM and the IEEE. He has received the NSF Career Award, an IBM Faculty Award, the Okawa Fundantion Research Grant, and a Noyce Family Faculty Scholarship.